A typical integrated circuit (IC) design may be composed of millions of interdependent and interconnected design components (e.g., logic gates, switches, memory cells, buffers, inverters, amplifiers and the like). Creating and verifying a design can consume tremendous amounts of labor-hours and computational resources. Typically, an IC is designed using a computer-aided design (CAD) tool that converts a low-level design description (e.g., a register transfer level description) or high-level design description (e.g., a Hardware Description Language or Verilog description) into a computer model of the IC. The model specifies what every bit of the circuit design does on every clock cycle, and constitutes a logical modeling/verification step of the design. The physical design of the IC takes the logical model of the IC (e.g., RTL model) and a library of design cells (e.g., logic gates), and creates a chip design. This involves figuring out which gates to use, defining physical locations for them and wiring them together. Then, the design is validated by design rule checking and by simulating the performance of the design in a computer model. When problems in the design are identified, there may be a large number of possible hardware modifications to address each problem. Each hardware modification must be tested to determine if the modification fixes the problem and if the modification creates any new problems. Each time a hardware modification is tested, the modification must be modeled and the operation of the modified design must be simulated again. Even if one localized change is made, either the entire design or an entire functional area of the design must be tested to determine the global effects of any the design change. For example, many designs have critical signal timing requirements and corresponding critical signal paths. If a modification is made to one signal path of the design, even a modification to a non-critical signal path, the effect of the modification must be computed for every other signal path to determine if new critical signal paths have been created and whether they meet performance requirements.
In the past, when designs were limited to, perhaps, thousands of elements and interconnections, or even hundreds of thousands, the time and cost of multiple modifications and simulations may have been acceptable. Currently, however, the number of elements, interconnects and signals in a typical design may reach many hundreds of millions. The conventional method of implementing the entire design and then addressing design problems is now very time consuming and to some extent ineffective. For example, IC manufacturing processes are variable and conventional IC design tools make assumptions about the statistics of the variations. In an IC with 10 million signals, for example, a 0.1% error rate can translate to 10,000 design issues that need to be addressed. Addressing this number of problems is very time consuming at best, and prohibitively expensive at worst. And, as noted above, because a design change in one region of the IC can impact performance anywhere else, often the entire design must be reevaluated. Even a slight modification in which one elemental design component is added, modified, or removed, may propagate widely through the design and significantly affect the overall behavior of the design.
Given that there can be a large number of design issues in a complex IC design, that each design issue may have many possible solutions, and that each possible solution may create other design issues, the total number of design iterations may be astronomical. To address this problem, various techniques have been proposed that attempt to reduce the amount of computation required. These techniques are based on limiting and/or identifying the boundaries of the design beyond which the effects of a design modification can be disregarded. Even when such techniques are employed, however, the analysis of multiple proposed modifications on an individual basis is still time consuming, computationally extensive and costly.
For example, a timing violation might be addressed by adding or removing a buffer stage or altering a signal amplitude to shift an edge trigger point. This, of course, has a propagating effect which extends beyond the improved timing of a single stage in the timing path. As the changed delay or amplitude of the signal propagates throughout the portion of the design influenced by the modification, the modification impacts the timing at each stage, which may change the critical paths for the entire design.
Conventional methods for validating such design changes would require another round of physical design and simulation. Therefore, evaluating a range of signal strength changes or a range of potential buffer sizes to determine the optimal value required to resolve the timing violation could be prohibitively expensive.